Method for forming metal wiring in semiconductor device

ABSTRACT

Disclosed is a method for forming a metal wiring in a semiconductor device in order to improve the operational speed of the semiconductor device. The method includes the steps of depositing an interlayer dielectric film on a silicon substrate, in which the interlayer dielectric film has a contact hole for exposing a predetermined portion of the silicon substrate, depositing a barrier layer on the interlayer dielectric film having the contact hole, depositing a first tungsten layer on the barrier layer by using SiH 4  as a reaction gas, depositing a second tungsten layer on the first tungsten layer by using B 2 H 6  as a reaction gas, depositing a third tungsten layer on the second tungsten layer in such a manner that the contact hole is filled with the third tungsten layer, and selectively etching the third tungsten layer, the second tungsten layer, the first tungsten layer, and the barrier layer, thereby forming the metal wiring.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for fabricating asemiconductor device, and more particularly to a method for forming ametal wiring in a semiconductor device in order to improve anoperational speed of the semiconductor device.

2. Description of the Prior Art

As generally known in the art, aluminum or tungsten is mainly used as amaterial for a metal wiring. In particular, since a tungsten layer,which is deposited on a substrate through a chemical vapor deposition(CVD) process, represents the superior gap-filling characteristic andthe low resistivity, the tungsten layer is mainly used for fabricatinghighly integrated semiconductor devices.

FIGS. 1 a and 1 b are cross-sectional views illustrating a conventionalprocedure for forming a metal wiring in a semiconductor device.

As shown in FIG. 1 a, an interlayer dielectric film 11 is formed on asilicon substrate 10 having a predetermined base structure and a contacthole 12 for exposing a predetermined portion of the silicon substrate 10is formed by selectively etching the interlayer dielectric film 11. Inaddition, a barrier layer 13 is formed on the interlayer dielectric film11 including the contact hole 12. The barrier layer 13 has a stackedstructure including a Ti layer and a TiN layer stacked on the Ti layer.Then, the silicon substrate 10 formed with the barrier layer 13 issubject to the rapid heat-treatment process, thereby forming a TiSi_(x)layer 14 on an interfacial surface between the barrier layer 13 and thesilicon substrate 10.

After that, a first tungsten layer 15 is formed on the barrier layer 13.When forming the first tungsten layer 15 on the barrier layer 13, WF₆ isused as a source gas and SiH₄ is used as a reaction gas for the firsttungsten layer 15. Then, a second tungsten layer 16, that is, a tungstenbulk layer is formed on the first tungsten layer 15 in such a mannerthat the contact hole 12 is filled with the second tungsten layer 16.When forming the second tungsten layer 16 on the first tungsten layer15, WF₆ is used as a source gas and H₂ is used as a reaction gas for thesecond tungsten layer 16.

As shown in FIG. 1 b, a metal wiring 17 is formed by selectively etchingthe second tungsten layer 16, the first tungsten layer 15, and thebarrier layer 13. Reference numerals 13 a, 15 a and 16 a represent aremaining barrier layer, a remaining first tungsten layer and aremaining second tungsten layer, respectively, which may remain afterthe etching process has been completed.

However, as the integration degree of the semiconductor device has beenincreased, the conventional procedure for forming the metal wiring 17 inthe semiconductor device represents a limitation to reduce theresistance of the metal wiring 17 even if tungsten having the lowresistivity is used as a material for the metal wiring 17. For thisreason, the operational speed of the semiconductor device issignificantly reduced.

SUMMARY OF THE INVENTION

Accordingly, the present invention has been made to solve theabove-mentioned problems occurring in the prior art, and an object ofthe present invention is to provide a method for forming a metal wiringin a semiconductor device in order to improve an operational speed ofthe semiconductor device by reducing the resistance of the metal wiringcorresponding to the integration degree of the semiconductor device.

In order to accomplish the above object, according to the presentinvention, there is provided a method for forming a metal wiring in asemiconductor device, the method comprising the steps of: depositing aninterlayer dielectric film on a silicon substrate, the interlayerdielectric film having a contact hole for exposing a predeterminedportion of the silicon substrate; depositing a barrier layer on theinterlayer dielectric film having the contact hole; depositing a firsttungsten layer on the barrier layer by using SiH₄ as a reaction gas;depositing a second tungsten layer on the first tungsten layer by usingB₂H₆ as a reaction gas; depositing a third tungsten layer on the secondtungsten layer in such a manner that the contact hole is filled with thethird tungsten layer; and selectively etching the third tungsten layer,the second tungsten layer, the first tungsten layer, and the barrierlayer, thereby forming the metal wiring.

According to the preferred embodiment of the present invention, thefirst and second tungsten layers are deposited through an ALD process ora CVD process.

According to the preferred embodiment of the present invention, thefirst and second tungsten layers are deposited in a thickness of about 1to 10 nm.

According to the preferred embodiment of the present invention, thedeposition steps for the first and second tungsten layers are repeateduntil the first and second tungsten layers have a desired thickness,respectively.

According to the preferred embodiment of the present invention, oneselected from the group consisting of H₂, SiH₄, and a mixture gasthereof is used as a reaction gas for the third tungsten layer.

According to the preferred embodiment of the present invention, thefirst to third tungsten layers are deposited by using a W-containing gasas a source gas therefor, and the W-containing gas is one selected fromthe group consisting of WF₆, WCl₆, WBr₆, W(Co)₆, W(C₂H₂)₆, W(PF₃)₆,W(allyl)₄, (C₂H₅)WH₂, [CH₃(C₅H₄)]₂WH₂, (C₂H₅)W(CO)₃(CH₃), W(butadiene)₃,W(methylvinyl-ketone)₃, (C₅H₅)HW(CO)₃, (C₇H₈)W(CO)₃, and(1,5-COD)W(CO)₄.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will be more apparent from the following detailed descriptiontaken in conjunction with the accompanying drawings, in which:

FIGS. 1 a and 1 b are cross-sectional views illustrating a conventionalprocedure for forming a metal wiring in a semiconductor device;

FIGS. 2 a to 2 e are cross-sectional views illustrating a procedure forforming a metal wiring in a semiconductor device according to oneembodiment of the present invention;

FIGS. 3 a and 3 b are SEM micrographs illustrating grain size andmicrostructure of tungsten bulk layers grown on ALD-tungsten layersdeposited by using SiH₄ and B₂H₆ as reaction gases, respectively; and

FIG. 4 is a graph illustrating the resistivity of a stacked structure ofan ALD-tungsten layer and a tungsten bulk layer as a function ofALD-tungsten film thickness.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, the present invention will be described with reference toaccompanying drawings.

FIGS. 2 a to 2 e are cross-sectional views illustrating a procedure forforming a metal wiring in a semiconductor device according to oneembodiment of the present invention.

As shown in FIG. 2 a, an interlayer dielectric film 21 is deposited on asilicon substrate 20 having a predetermined base structure and a contacthole 22 for exposing a predetermined portion of the silicon substrate 20is formed by selectively etching the interlayer dielectric film 21. Inaddition, a barrier layer 23 is deposited on the interlayer dielectricfilm 21 including the contact hole 22. The barrier layer 23 has astacked structure including a Ti layer and a TiN layer stacked on the Tilayer. Then, the silicon substrate 20 formed with the barrier layer 23is subject to the rapid heat-treatment process, thereby forming aTiSi_(x) layer 24 on an interfacial surface between the barrier layer 23and the silicon substrate 20.

As shown in FIG. 2 b, a first tungsten layer 25 is deposited on thebarrier layer 23. When forming the first tungsten layer 25 on thebarrier layer 23, WF₆ is used as a source gas and SiH₄ is used as areaction gas for the first tungsten layer 25. The first tungsten layer25 is deposited on the barrier layer 23 with a thickness of about 1-10nm through an ALD (atomic layer deposition) process. The ALD processincludes a SiH₄ gas dosing step, a purge step, a WF₆ gas dosing step,and a purge step, which are sequentially performed and repeated untilthe first tungsten layer 25 having a desired thickness can be obtained.At this time, SiH₄, which is a reaction gas for the first tungsten layer25, may be fed in the form of gas or plasma. Instead of SiH₄, Si₂H₆ canbe used as a reaction gas for the first tungsten layer 25.

As shown in FIG. 2 c, a second tungsten layer 26 is deposited on thefirst tungsten layer 25. When forming the second tungsten layer 26 onthe first tungsten layer 25, WF₆ is used as a source gas and B₂H₆ isused as a reaction gas for the second tungsten layer 26. The secondtungsten layer 26 is deposited on the first tungsten layer 25 with athickness of about 1-10 nm through the ALD process. The ALD processincludes a B₂H₆ gas feeding step, a primary purge step, a WF₆ gasfeeding step, and a secondary purge step, which are sequentiallyperformed and repeated until the second tungsten layer 26 having adesired thickness can be obtained. At this time, B₂H₆, which is areaction gas for the second tungsten layer 26, may be fed in the form ofgas or plasma. In addition, after depositing the second tungsten layer26, a deposition cycle can be repeated in order to sequentially depositthe first and second tungsten layers 25 and 26 until the first andsecond tungsten layers 25 and 26 have a desired thickness. The first andsecond tungsten layers 25 and 26 can be deposited through a CVD process.

Referring to FIG. 2 d, a third tungsten layer 27, that is, a tungstenbulk layer is deposited on the second tungsten layer 26 through the CVDprocess in such a manner that the contact hole 22 is filled with thethird tungsten layer 27. When forming the third tungsten layer 27 on thesecond tungsten layer 26, WF₆ is used as a source gas and one selectedfrom the group consisting of H₂, SiH₄, and a mixture gas thereof is usedas a reaction gas for the third tungsten layer 27. Instead of WF₆, oneselected from the group consisting of WCl₆, WBr₆, W(Co)₆, W(C₂H₂)₆,W(PF₃)₆, W(allyl)₄, (C₂H₅)WH₂, [CH₃(C₅H₄)]₂WH₂, (C₂H₅)W(CO)₃(CH₃),W(butadiene)₃, W(methylvinyl-ketone)₃, (C₅H₅)HW(CO)₃, (C₇H₈)W(CO)₃, and(1,5-COD)W(CO)₄ can be used as a source gas for the third tungsten layer27.

As shown in FIG. 2 e, a metal wiring 28 is formed by selectively etchingthe first and second tungsten layer 25 and 26 and the barrier layer 23.Reference numerals 23 a, 25 a, 26 a and 27 a represent a remainingbarrier layer, a remaining first tungsten layer, a remaining secondtungsten layer and a remaining third tungsten layer, respectively, whichmay remain after the etching process has been completed.

As described above, after depositing the first tungsten layer 25 on thebarrier layer 23 by using the SiH₆ gas as a reaction gas for the firsttungsten layer 25, the second tungsten layer 26 is deposited on thefirst tungsten layer 25 by using the B₂H₆ gas as a reaction gas for thesecond tungsten layer 26. Then, the third tungsten layer 27, that is,the tungsten bulk layer is deposited on the second tungsten layer 26, sothat the tungsten bulk layer of the present invention has a grain sizelarger than that of the conventional tungsten bulk layer. The reasonwill be described below with reference to FIGS. 3 a, 3 b and 4.

FIG. 3 a is an SEM micrographs illustrating the grain size of aCVD-tungsten bulk layer grown through a CVD process from an ALD-tungstenlayer deposited by using SiH₄ as the reaction gas.

FIG. 3 b is an SEM photographic view illustrating the structure of aCVD-tungsten bulk layer grown through a CVD process on an ALD-tungstenlayer deposited by using B₂H₆ as the reaction gas and FIG. 4 is a graphillustrating the resistivity of a stacked structure of the ALD-tungstenlayer and the CVD-tungsten bulk layer as a function of ALD-tungsten filmthickness.

As can be seen from FIGS. 3 a and 3 b, the grain size of theCVD-tungsten bulk layer grown on the ALD-tungsten layer deposited byusing B₂H₆ as the reaction gas is significantly larger than the grainsize of the CVD-tungsten bulk layer grown on the ALD-tungsten layerdeposited by using SiH₄ as the reaction gas. As shown in FIG. 4, if thetungsten layer has a larger grain size, the resistivity of the tungstenlayer can be reduced on the same thickness condition thereof. Forinstance, if a tungsten bulk layer is grown from an ALD-tungsten layerdeposited by using B₂H₆ as a reaction gas, the resistivity of a stackedstructure including the ALD-tungsten layer with a thickness of about 10nm and the CVD-tungsten layer with a thickness of about 200 nm may bereduced by about 20% as compared with the resistivity of a stackedstructure in which a tungsten bulk layer is grown on a ALD-tungstenlayer deposited by using SiH₄ as a reaction gas.

In the meantime, if the ALD-tungsten layer is deposited by using B₂H₆ asthe reaction gas, the deposition rate of the ALD-tungsten layer is ofabout 2.5 to 3 Å/cycle, and if the ALD-tungsten layer is deposited byusing SiH₄ as the reaction gas, the deposition rate of the ALD-tungstenlayer is of about 10 Å/cycle. That is, the deposition rate for theALD-tungsten layer may be lowered if the ALD-tungsten layer is onlydeposited by using B₂H₆ as the reaction gas. For this reason, accordingto the present invention, after sequentially depositing the first andsecond tungsten layers 25 and 26 by using SiH₄ and B₂H₆, respectively,the third tungsten layer 27, that is, the tungsten bulk layer isdeposited on the second tungsten layer 26. In this case, the metalwiring 28 having the large-sized grain can be obtained. Therefore, it ispossible to reduce the resistance of the metal wiring 28. In addition,since the second tungsten layer 26 is deposited on the first tungstenlayer 25 by using B₂H₆ as the reaction gas after rapidly depositing thefirst tungsten layer 25 by using SiH₄ as the reaction gas, it ispossible to rapidly obtain the tungsten layers having a desiredthickness.

As described above, according to the present invention, the first andsecond tungsten layers 25 and 26 are sequentially deposited by usingSiH₄ and B₂H₆ as a reaction gas, respectively. After that, the tungstenbulk layer is deposited on the second tungsten layer, thereby enlargingthe grain size of the tungsten bulk layer. Therefore, the resistance ofthe metal wiring in the stacked structure can be reduced and theoperational speed of the semiconductor device can be improved.

Although a preferred embodiment of the present invention has beendescribed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims.

1. A method for forming a metal wiring in a semiconductor device, themethod comprising the steps of: i) depositing an interlayer dielectricfilm on a silicon substrate, the interlayer dielectric film having acontact hole for exposing a predetermined portion of the siliconsubstrate; ii) depositing a barrier layer on the interlayer dielectricfilm having the contact hole; iii) depositing a first tungsten layer onthe barrier layer by using SiH₄ as a reaction gas; iv) depositing asecond tungsten layer on the first tungsten layer by using B₂H₆ as areaction gas; v) depositing a third tungsten layer on the secondtungsten layer in such a manner that the contact hole is filled with thethird tungsten layer; and vi) selectively etching the third tungstenlayer, the second tungsten layer, the first tungsten layer, and thebarrier layer, thereby forming the metal wiring.
 2. The method asclaimed in claim 1, wherein the first and second tungsten layers aredeposited through an ALD process or a CVD process.
 3. The method asclaimed in claim 1, wherein the first and second tungsten layers aredeposited in a thickness of about 1 to 10 nm.
 4. The method as claimedin claim 1, further comprising a step of repeating steps iii) and iv)until the first and second tungsten layers have a desired thickness,respectively.
 5. The method as claimed in claim 1, wherein one selectedfrom the group consisting of H₂, SiH₄, and a mixture gas thereof is usedas a reaction gas for the third tungsten layer.
 6. The method as claimedin claim 1, wherein the first to third tungsten layers are deposited byusing a W-containing gas as a source gas therefor, and the W-containinggas is one selected from the group consisting of WF₆, WCl₆, WBr₆,W(Co)₆, W (C₂H₂)₆, W (PF₃)₆, W(allyl)₄, (C₂H₅) WH₂, [CH₃(C₅H₄)]₂WH₂,(C₂H₅)W(CO)₃(CH₃), W(butadiene)₃, W(methylvinyl-ketone)₃, (C₅H₅)HW(CO)₃,(C₇H₈)W(CO)₃, and (1,5-COD)W(CO)₄.